The invention relates to a method of manufacturing a semiconductor device comprising a semiconductor body which is provided at a surface with a transistor having a gate insulated from a channel region at the surface of the semiconductor body by a gate dielectric, the gate having an area, by which method an active region of a first conductivity type adjoining the surface is defined in the semiconductor body, and a patterned layer is applied defining the area of the planned gate to be provided at a later stage of the process, after which a dielectric layer is applied, which dielectric layer is provided with a recess at the area of the planned gate by removing the patterned layer, after which impurities are introduced via the recess into the channel region of the semiconductor body in a self-registered way by using the dielectric layer as a mask, and an insulating layer is applied, forming the gate dielectric of the transistor, on which insulating layer a conductive layer is applied thereby filling the recess, which conductive layer is shaped into the gate of the transistor.
A method of manufacturing a semiconductor device of the kind mentioned in the opening paragraph is known from U.S. Pat. No. 5,773,348. In the known method, a stacked pad oxide/nitride layer is formed on a surface of the semiconductor body, on which stacked pad oxide/nitride layer a patterned photoresist layer is applied, forming the area of the gate planned, hereinafter also called the planned gate area. An oxide layer is selectively deposited on the stacked pad oxide/nitride layer, after which the patterned photoresist layer is removed. In a subsequent implantation process, impurities are introduced via the planned gate area into the semiconductor body by using the oxide layer as an ion implantation mask, thereby providing the semiconductor body with an anti-punchthrough impurity region. Then, nitride spacers are formed within the planned gate area at the sidewalls of the oxide layer and the stacked pad oxide/nitride layer is removed within the same region. A gate oxide layer is subsequently applied within the planned gate area, followed by the deposition of an amorphous silicon layer filling the planned gate area, which amorphous silicon layer is shaped into the gate of the transistor. Finally, the oxide layer and the underlying stacked pad oxide/nitride layer are removed and a salicide process including a two-stage annealing treatment with temperatures as high as 750 to 900xc2x0 C. is carried out in order to form self-aligned contacts and shallow junction source and drain zones.
Whether impurities are introduced into the semiconductor body by means of diffusion from a chemical source provided at the surface of the semiconductor body or by means of ion implantation, in both cases a high-temperature annealing treatment with temperatures as high as about 900xc2x0 C. needs to be carried out.
A disadvantage of the known method is that the formation of the gate and the introduction of the impurities via the planned gate area into the semiconductor body take place prior to the formation of the source zone and the drain zone and, hence, prior to the high-temperature two-stage annealing treatment. Because the gate is subjected to the high temperatures of this annealing treatment, serious constraints are imposed on the choice of process compatible materials for the gate. Moreover, the high-temperature anneal will also adversely redistribute the impurities that have been locally introduced into the semiconductor body for punchthrough suppression.
It is an object of the invention to provide a method of manufacturing a semiconductor device of the kind mentioned in the opening paragraph, which increases the flexibility as regards the implementation of process compatible materials for the gate in a conventional CMOS process flow, and which allows a local introduction of impurities via the planned gate area into the semiconductor body without an adverse redistribution of the introduced impurities at a later stage of the process.
According to the invention, this object is achieved in that the patterned layer consisting of refractory material is applied, which patterned layer acts as a mask during the formation of a source zone and a drain zone of a second conductivity type in the semiconductor body, after which the dielectric layer is applied in a thickness which is sufficiently large to cover the patterned layer, which dielectric layer is removed over part of its thickness by means of a material removing treatment until the patterned layer is exposed, which patterned layer is then removed.
The above-stated measures in accordance with the invention prevent the gate as well as the impurities, which have been locally introduced into the semiconductor body via the recess at the planned gate area, from being exposed to the high temperatures of the annealing treatment associated with the formation of the source zone and the drain zone of the transistor. In this way, the flexibility as regards the use of process compatible materials for the gate is substantially increased, and redistribution of the locally introduced impurities is counteracted.
The planned gate area is defined by depositing a patterned layer, which is composed of refractory material to withstand the high temperatures of the annealing treatment associated with the subsequent formation of the source zone and the drain zone of the transistor. Prior to the removal of the patterned layer, a relatively thick dielectric layer is applied in a thickness which is sufficiently large to cover the patterned layer. The dielectric layer is subsequently removed over part of its thickness by means of, for example, chemical-mechanical polishing until the patterned layer is exposed, which patterned layer is removed by means of selective etching, thereby providing the dielectric layer with a recess at the planned gate area. After the removal of the patterned layer, a dip-etch may be carried out in order to remove a surface layer composed of, for instance, silicon oxide, which may have been advantageously applied to the surface of the semiconductor body in order to protect the semiconductor body against contamination. Impurities are then introduced via the recess into the channel region of the semiconductor body in a self-registered way using the dielectric layer as a mask. Either before or after the introduction of the impurities, an insulating layer is applied, forming the gate dielectric of the transistor. Then, a conductive layer is applied, which fills the recess and is shaped into the gate of the transistor.
The impurities may be introduced into the channel region of the semiconductor body by means of a diffusion process, involving two steps in general. First, the impurities are placed on or near the surface of the semiconductor body by a gaseous deposition step or by coating the surface with a layer containing the desired impurities. This is followed by an annealing treatment in order to further drive-in the impurities into the semiconductor body by means of diffusion. An alternative to the diffusion process is ion implantation. The desired impurities are first ionized and then accelerated by an electric or magnetic field to a high energy level, typically in the range from 1 to 500 keV. A beam of the accelerated high-energy ions strikes the surface of the semiconductor body and penetrates exposed regions thereof. The penetration is typically less than a micrometer below the surface, and considerable damage is done to the crystal lattice during implantation. Consequently, an annealing treatment is required in order to repair the damage the crystal lattice, and to activate the as-implanted impurities.
Due to its ability to more precisely control the number of impurities introduced into the semiconductor body, ion implantation is preferred to diffusion. Moreover, ion implantation allows impurity introduction into the semiconductor body with much less lateral distribution than via diffusion and, hence, allows devices to be manufactured with features of smaller dimensions.
For MOS transistors with channel lengths below about 2 xcexcm, short-channel effects start to play an important role in respect of device behavior. In this respect, particularly the short-channel effects known as punchthrough and short-channel threshold-voltage shift become dominant.
Punchthrough is a phenomenon associated with the merging of the depletion regions of the source zone and the drain zone. That is, as the channel gets shorter, the space between the edges of the depletion regions becomes smaller, provided the channel-region doping is kept constant as the channel length decreases. When the channel length becomes approximately equal to the sum of the widths of the depletion regions of the source zone and the drain zone, punchthrough is established.
Experimentally, it is observed that, as the channel length decreases to less than about 2 xcexcm, the threshold voltage shifts to below the long-channel values, which effect is referred to as the short-channel threshold-voltage shift. The fraction of the depletion charge within the channel region under the gate, which is induced by the source zone and the drain zone, is insignificant for long-channel transistors, but becomes significant for short-channel transistors whose channel length approaches the sum of the widths of the depletion regions of the source zone and the drain zone. Consequently, less charge is needed to cause inversion, and the threshold voltage is reduced.
On the above grounds, it is advantageous to provide the channel region of a short-channel transistor with an impurity region for threshold voltage correction and/or punchthrough suppression. In order to reach these effects, the doping of the semiconductor body within the channel region under the gate generally has to be increased. Impurities for threshold voltage correction and/or punchthrough suppression can be implanted into the channel region substantially perpendicularly to the surface of the semiconductor body. However, in order to counteract channeling of the impurities along crystal directions and planes, it is advantageous to implant the impurities into the channel region at a small angle of a few, for instance seven, degrees with the normal to the surface of the semiconductor body by tilting the semiconductor body before implantation. It is to be noted that an implantation for punchthrough suppression in general leads to an increase of the threshold voltage as well.
Conventionally, the impurities for threshold voltage correction and/or punchthrough suppression are implanted after definition of active regions adjoining the surface of the semiconductor body and after application of a gate oxide layer covering the entire surface of the semiconductor body. In this way, the introduced impurities are laterally distributed over the entire active regions, and counter-doping is required for subsequent formation of source and drain zones in regions adjoining the surface of the semiconductor body. The need of counter-doping for source zone and drain zone formation is counteracted by the method of the invention by locally implanting the above-mentioned impurities via the recess into the channel region of the transistor only.
If the impurities for threshold voltage correction and/or punchthrough suppression are implanted via the recess, substantially perpendicularly to the surface or at a small angle of a few degrees with the normal to the surface of the semiconductor body, the channel region is implanted over practically its entire length, thereby increasing the threshold voltage throughout the range of channel lengths. Consequently, when a process flow for semiconductor devices comprising both long-channel and short-channel transistors is optimized in such a way that the short-channel transistors can operate at a nominal threshold voltage, the long-channel transistors inevitably obtain a higher threshold voltage as well. In order to provide the channel region only partially, that is to say at its edges, with impurities and, hence, suppress the increase of the threshold voltage for long-channel transistors, it is advantageous to implant the impurities at an acute angle with the normal to the surface of the semiconductor body. Obviously, the maximum angle at which the impurities can be implanted into the channel region is dependent on the aspect ratio of the recess in the dielectric layer.
The patterned layer defining the planned gate area and being composed of refractory material, may comprise, for instance, silicon nitride or aluminum oxide. However, in order to match the process flow to conventional CMOS processing, the patterned layer applied advantageously comprises silicon. In this respect, polycrystalline silicon, or possibly amorphous silicon or GexSi(1xe2x88x92x) may be applied, with the fraction of germanium x lying in the range between 0 and 1.
Experimentally, it is observed that the moment of stopping the chemical-mechanical polishing (CMP) of the dielectric layer is rather critical if the patterned layer is composed of silicon. If the CMP process is stopped too early, oxide residue is left on the patterned layer, which hinders the subsequent removal of the patterned layer. If the CMP process is carried on too long, the definition of the height of the planned gate is adversely affected. In order to improve the height definition of the process, it is preferred to apply the patterned layer as a double-layer including a first sub-layer comprising the silicon and on top thereof, a second sub-layer composed of a material having a larger resistance to the material removing treatment than silicon and being selectively etchable with respect to the dielectric layer. Thus, the second sub-layer will act as an etch stop layer during the removal of the dielectric layer. In this respect it is advantageous to apply silicon nitride as the second sub-layer and silicon oxide as the dielectric layer. Alternatively, aluminum oxide can be used instead of silicon nitride and/or BPSG (borophosphosilicate glass) instead of silicon oxide. The second sub-layer is selectively removed from the first sub-layer, after which the first sub-layer is selectively removed. After the introduction of the impurities via the recess into the channel region of the semiconductor body and the application of the insulating layer forming the gate dielectric, the conductive layer is applied thereby filling the recess. In order to obtain a compact gate structure of the transistor, the conductive layer is preferably shaped into the gate by maskless removal of said layer until either the insulating layer or the dielectric layer is exposed. In this way the gate is recessed in the dielectric layer. The above mentioned maskless removal of the conductive layer is preferably accomplished by means of chemical-mechanical polishing (CMP). A subsequent maskless removal of the insulating layer is not required, but can be beneficial in case the insulating layer comprises a high-dielectric constant material.
The gate of the transistor and, hence, the conductive layer from which it is formed, advantageously comprises a metal instead of conventional polycrystalline silicon. In contrast with polycrystalline silicon, metals intrinsically have a relatively low resistance and do not suffer from detrimental depletion effects. In this respect a low-resistance metal such as aluminum, tungsten, copper or molybdenum can be advantageously applied. In case a metal is used, the conductive layer is preferably applied as a double-layer including a layer comprising the metal and, on top thereof, a layer acting as adhesion layer and/or barrier layer. In this respect titanium (Ti) may be applied as adhesion layer and titanium nitride (TiN) or titanium tungsten (TiW) as barrier layer. It is to be noted that application of a metal gate in the prior art method would lead to melting in the case of an aluminum gate or cause detrimental interaction between the metal gate and the gate dielectric upon exposure to the high temperatures of the annealing treatment associated with the formation of the source zone and the drain zone of the transistor. In the method of the present invention the gate, once formed, is not exposed to high temperatures at subsequent stages of the process flow.
In order to improve the performance of the transistor, it may be advantageous to apply a dielectric material with a dielectric constant higher than that of silicon oxide (xcex5xcx9c4) as the gate dielectric and, hence, as the insulating layer from which the latter is formed. In this respect, tantalum oxide (Ta2O5; xcex5xcx9c20-25), aluminum oxide (Al2O3; xcex5xcx9c10) or silicon nitride (Si3N4xcex5xcx9c7) can be applied to advantage, as these materials are deposited in a conformal and reproducible way by means of chemical vapor deposition (CVD). It is to be noted that application of a gate dielectric composed of a high dielectric constant material in the prior art method may lead to degradation of the dielectric properties of the material upon exposure to the high temperatures of the annealing treatment associated with the formation of the source zone and the drain zone of the transistor. In the method of the present invention, the gate dielectric, once formed, is not exposed to such high temperatures at subsequent stages of the process flow.